Digital image processing has become very commonly used and is important in many fields. Digital image processing acquires an image from a sensor and transforms the image to viewable content. However, digital image processing, including multi-frame image processing, can require significant resources of an image processing device, such as a digital camera that may be implemented in a portable computer or communication device. When accessing data of a frame or multiple frames captured by an image processing device, the formatting of data is beneficial in reducing system latency and improving memory bandwidth. In modern SoCs, IPs typically access system memory (e.g. DDR) via a System MMU which provides contiguous (i.e. virtual) view of memory to the IPs and performs the virtual-to-physical address translation. The Virtual Address (VA) to Physical Address (PA) translation involves a first level translation lookup in the Translation Lookaside Buffer (TLB). A TLB is a memory cache that stores recent translations of virtual to physical addresses. When system needs to access memory using a physical address, it first checks if a virtual to physical address translation exists in the memory cache (TLB). If a translation is found, it is referred to as a “TLB hit”. If it is not found, the system has to look for the physical mapping in the operating system's page table. This process is referred to as a “page table walk”. Since this page table is in DRAM, it is a high latency and bandwidth intensive operation. To meet the high bandwidth requirements and avoid the additional memory latency incurred due to page table walk, it is important to achieve a TLB hit as much as possible. For example, the TLB hit rate is higher if tiles are fetched in raster order from left to right. However, if tiles need to be fetched from top to bottom, it will result in frequent cache misses. Frequent cache misses increase memory access latency since page entries are fetched from system memory, such as a dynamic random access memory (DRAM).
Accordingly, devices and methods that improve the processing of digital images, and more particularly devices and methods that reduce the number of TLB cache misses and the latency of memory accesses, are beneficial.